1. Field of the Invention
The present invention relates to a microprocessor with a power consumption which can be reduced by changing the frequency of an internal clock signal of a PLL ("Phase-Locked Loop") section in accordance with a microprocessor usage condition.
In recent years, small-sized apparatuses, such as portable devices, in which microprocessors are used, have become increasingly popular. Therefore, it has been required to reduce the power consumption in the microprocessor.
In general, a microprocessor includes a PLL section for generating an internal clock signal in response to an external clock signal, and a processor for executing an instruction in response to the internal clock signal supplied from the PLL section. Regarding microprocessors, there are two types: i.e., a built-in PLL section type in which the PLL section is mounted on a processor chip, and an external PLL section type in which the PLL section is arranged outside of the processor chip. The microprocessor referred to in this specification represents a microprocessor including a PLL section, regardless of whether it is the built-in PLL section type or the external PLL section type.
2. Description of the Related Art
As prior arts, a Japanese Laid Open Patent Publication (Kokai) No. 59-122223 and an international publication WO85/02275 disclose a PLL section which outputs a clock signal which is divided by a processor to lower the frequency of the clock signal used in the processor, so as to reduce the power consumption. In these prior arts, however, the frequency of the clock signal for operating the PLL section is fixed to the maximum frequency, so that the power consumption in the PLL section is still large.
Therefore, in the prior art microprocessor, even though the operating speed of the processor itself is lowered to reduce the power consumption, there is a disadvantage in that the power consumption in the PLL section is still large.